The present invention relates to mask-programmable logic devices, and more particularly, to methods of creating a mask-programmed logic device from a pre-existing circuit design.
Programmable logic devices (PLDs) are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing” (i.e., opening) fusible links. Alternatively, configuration may have been stored in a programmable read-only memory. These devices generally provided a user with the ability to configure the devices for “sum-of-products” (or “P-TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration information in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provided the user with the ability to configure the devices for look-up table-type logic operations. At some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory (RAM), read-only memory (ROM), or logic (such as P-TERM logic).
In all of the foregoing programmable logic devices, both the logic functions of particular logic resources in the device, and the interconnect resources for routing of signals between the logic resources, were programmable. Alternatively, mask-programmable logic devices (MPLDs) have been provided. With mask-programmable logic devices, instead of selling all users the same device, a manufacturer produces a mask-programmable base device with a standardized arrangement of logic resources whose functions are not programmable by the user, and which lacks any routing or interconnect resources.
The user provides the manufacturer of the mask-programmable logic device with the specifications of a desired device, which may be the configuration information file for programming a comparable conventional programmable logic device (“source PLD”). The manufacturer uses that information to add metallization layers to the base device described above. Those additional layers program the base device's logic resources by making certain fixed connections within the resources based on the configuration information of the configurable memory (CRAM) cells of the source device (i.e., by hard coding the configuration values provided by the user's information file to power sources of the MPLD). Furthermore, these additional layers add interconnect resources for routing between the logic resources. Mask-programmable logic devices can also be provided with embedded random access memory blocks, as described above in connection with conventional programmable logic devices. In such mask-programmable logic devices, if the embedded memory is configured as read-only memory or P-TERM logic, that configuration is also accomplished using the additional metallization layers.
While conventional programmable logic devices allow a user to easily design a device to perform a desired function, they invariably include resources that may not be used for a particular design. Moreover, in order to accommodate general purpose routing and interconnect resources, and switching resources that allow signals from any logic resource to reach any desired routing and interconnect resource, conventional PLDs grow ever larger as more functionality is built into them, increasing the size and power consumption of such devices. The routing of signals through the various switching resources as they travel from one routing and interconnect resource to another also slows down signals.
The advent of mask-programmable logic devices has allowed users to prove a design in a conventional source programmable logic device, but to commit the production version to a mask-programmable logic device, which, for the same functionality, can be significantly smaller and use significantly less power, because only the interconnect and routing resources actually needed for the particular design are added to the base device. In addition, there are no general purpose switching resources consuming space or power or slowing down signals. Such implementation of a pre-existing design of a source PLD on a mask-programmable base device are described, for example, in commonly-assigned U.S. patent application Ser. No. 10/113,838, filed Mar. 29, 2002, which is hereby incorporated by reference herein in its entirety.
Such MPLDs may obtain significant die size advantage compared to the source PLD through removal of all the programmability of the source device, including signal interconnect, signal routing configuration-related logic, and configuration memories. The base device architecture of such MPLDs may be almost identical to the source device, except for the routing structures. The organization of logic resources on the base devices of such MPLDs may be different from that of associated source devices, but these resources may be identical in functionality, quantity, accessibility, and structure, therefore allowing a direct conversion of resource-for-resource from the equivalent source device to the base device.
The removal of the pre-existing signal interconnect, signal routing configuration-related logic, configuration memories, and certain signal buffers of the source device from such MPLDs may provide significant size reduction of the die and may optimize signal routing. However, although the interconnection routing and the CRAM configuration values of the logic resources are hard coded in the physical design of such MPLDs by adding metallization layers to the base device, the configuration-related logic circuitry of the logic resources of the source device are maintained on the base device to minimize design changes and project development time. These configuration-related logics include a significant amount of transistor circuitry which increases the size and power consumption of such devices.
Accordingly, it would be desirable to provide improved techniques, systems, and methods for optimizing the area and performance of a mask-programmable logic device that implements a pre-existing circuit design and that requires minimal user involvement.